1. Field of the Invention
This invention relates generally to the cell structure, device configuration and fabrication process of power semiconductor devices. More particularly, this invention relates to a novel manufacturing processes with reduced masks by implementing improved termination configuration with trench contacts for both gate and source-body regions and multiple trench gates that are connected to the source-body regions in the termination areas thus preventing leakage currents.
2. Description of the Related Art
Conventional technologies for manufacturing semiconductor power devices are continuously challenged to further reduce the manufacturing cost by reducing the number of masks applied in the manufacturing processes. Furthermore, in attempt to miniaturize the device, the technologies are still faced with a limitation that prevents further increase of the cell density on a limited wafer surface area. Particularly, the limitations are caused by the wafer areas occupied by planar contacts and device configuration that may induce leakage currents thus leading to a breakdown voltage reduction.
Specifically, Wahl, et al. disclose in U.S. Pat. No. 6,462,376 a power MOSFET device that includes trenching floating rings with N+ source on top of the termination area as shown in FIG. 1A. The disclosures made in U.S. Pat. No. 6,462,376 are hereby incorporated by reference and FIG. 1A as included in this section is the same as FIG. 6 of U.S. Pat. No. 6,462,376. The potential of the trench gate that function as the floating rings may be higher than the source body region to induce a leakage current from the drain to the source because of the channel region is inverted to N type dopant. The leakage current thus leads to a lower breakdown voltage of the device. Darwish et al. discloses in U.S. Pat. No. 7,045,857 a trench device that includes trench gates in termination connected to the P-body region. However, as shown in FIG. 1B, the structures have planar contacts and such contacts are not suitable for device shrinkage with the planar contact occupies larger areas. Furthermore, the manufacturing processes of the device are much more complicate and applying more than four masks. The production cost is therefore increased when a device is configured according to the disclosures made by Darwish. Again, the disclosures made by Darwish in U.S. Pat. No. 7,045,857 are hereby incorporated by references and FIG. 1B as included in this section is the same as FIG. 29 of U.S. Pat. No. 7,045,857.
Therefore, there is still a need in the art of the semiconductor device fabrication, particularly for trenched power MOSFET design and fabrication, particularly in the termination area, to provide a novel cell structure, device configuration and fabrication process that would resolve these difficulties and design limitations. Specifically, it is desirable to maintain good electric contact to of trenched gate to the source body regions in the termination area to prevent a leakage current. Furthermore, it is very desirable to reduce the number of masks employed to manufacture the semiconductor power devices such that the above discussed difficulties and limitations may be resolved.